Unique inductor IP paves the way for RF and multi-gigabit transceivers at 20/16nm
San Jose, CA – Helic, Inc., the technology leader in EDA solutions for RF and high-speed IC design, announces today the availability of an IP library for spiral inductors at the 20 nanometer (nm) and 16nm technology nodes. The inductor library is already being used by a major semiconductor company in production design.
Addressing the needs of customers starting designs at 20/16nm, Helic developed a library of resizable, parametric inductor cells which are fully lithography-compliant, meeting the restrictive design rules of these advanced nodes. The increased number of Design Rule Checks (DRCs) at the 20/16nm nodes, threatened to prohibitively increase the design effort needed for inductor design. Helic’s solution completely eliminates the need for tedious and time-consuming manual layout, by fully automating the process of layout creation per designer specifications. The inductor layouts will comply with DRCs and meet all applicable lithography constraints (such as minimum density on each layer). The solution includes the automatic generation of dummy fill in the area taken up by a spiral.
Helic’s parametric inductor cells can be used in a variety of 20/16nm IC and SoC designs, including wireless RF transceivers, multi-gigabit transceivers, frequency synthesizers and clock/data recovery circuits. The company aims to drastically shorten the design cycles of such products, which typically employ a good number of integrated inductors for increased performance (e.g. low clock jitter, wide amplifier bandwidth, etc.).
The library of 20/16nm inductors comprises a variety of spiral geometries, such as square and octagonal, including differential and transformer configurations. All these cells can be easily resized to meet a wide range of inductance, quality factor, operating bandwidth and current handling specifications. Helic also offers inductor compiler tools to further automate layout synthesis and optimization.
Helic has been developing technology for silicon integrated inductor synthesis and modeling since 2000, and has been supplying its EDA software and solutions to numerous customers developing silicon products on technology nodes from 350nm, and now down to 20 and 16nm.
Helic, Inc. develops disruptive EDA technologies for RFIC and high-speed SoC design. We provide our customers with a comprehensive offering combining design tools, silicon IP and applications support, greatly reducing the development cycles of chips for wireless communications, broadband networking, PCs, tablets and other segments. We provide technology for rapid electromagnetics modeling, RF component synthesis, and signal integrity of silicon ICs and Systems-in-Package. Our solutions have been adopted by several major semiconductor companies since 2000.
Helic is headquartered at 2880 Zanker road, Suite 203, San Jose, CA 95134.
Press Contact: Nikolas Provatas T: +1-866-99-HELIC
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